The present invention relates to a power supply circuit for supplying a DC voltage to various electronic apparatuses, more particularly, to a charge pump circuit for boosting an input voltage.
In recent years, such a charge pump circuit has been used frequently as a power supply circuit capable of outputting a voltage higher than an input voltage without using an inductor, and supplying a power supply voltage to a load requiring a relatively small consumption current.
As this kind of charge pump circuit, for example, a power supply circuit described in Japanese Patent Application Laid-open No. 2003-348821 is proposed. FIG. 8 is a circuit diagram showing the charge pump circuit disclosed in Japanese Patent Application Laid-open No. 2003-348821. The charge pump circuit disclosed therein selects a voltage multiple ratio of 1, 1.5 or 2 depending on the drop of an input power supply voltage, boosts the input voltage and outputs the boosted voltage. In FIG. 8, a DC input power supply (not shown), such as a battery, supplies a DC input voltage Vi to the input terminal 10 of the charge pump circuit. Numerals 101 to 107 designate P-channel MOS transistors, and numerals 108 and 109 designate N-channel MOS transistors. The charge pump circuit is provided with a first flying capacitor 110 and a second flying capacitor 111. An output capacitor 112 outputs an output voltage Vo from the output terminal 20 of the charge pump circuit.
The drain of the P-channel MOS transistor 101, the source of the P-channel MOS transistor 102, one terminal of the P-channel MOS transistor 103, and the source of the P-channel MOS transistor 104 are connected to the input terminal 10. The source of the P-channel MOS transistor 101 is connected to the drain of the P-channel MOS transistor 105 and one terminal of the first flying capacitor 110. This connection point is referred to as a terminal P1. The drain of the P-channel MOS transistor 102 is connected to the drain of the P-channel MOS transistor 106, the other terminal of the first flying capacitor 110, and the drain of the N-channel MOS transistors 108. This connection point is referred to as a terminal P2. The other terminal of the P-channel MOS transistor 103 is connected to the source of the P-channel MOS transistor 106, one terminal of the second flying capacitor 111, and the drain of the P-channel MOS transistor 107. This connection point is referred to as a terminal P3. The drain of the P-channel MOS transistor 104 is connected to the other terminal of the second flying capacitor 111 and the drain of the N-channel MOS transistor 109. This connection point is referred to as a terminal P4.
The source of the P-channel MOS transistor 105 and the source of the P-channel MOS transistor 107 are connected to the output terminal 20, and the source of the N-channel MOS transistor 108 and the source of the N-channel MOS transistor 109 are grounded. Control signals S01 to S07 are applied to the gates of the P-channel MOS transistors 101 to 107, respectively. Control signals S08 and S09 are applied to the gates of the N-channel MOS transistors 108 and 109, respectively. Furthermore, a switch 113 is configured so that the back gate of the P-channel MOS transistor 103 can be switched to the side of the input terminal 10 or the side of the terminal P3 according to a control signal S10.
The circuit diagrams shown in FIGS. 9 to 11B are equivalent circuit diagrams each showing the state of each switch in each operation mode of the conventional charge pump circuit shown in FIG. 8. FIG. 9 shows the operation mode having a voltage multiple ratio of 1, FIGS. 10A and 10B show the operation mode having a voltage multiple ratio of 1.5, and FIGS. 11A and 11B show the operation mode having a voltage multiple ratio of 2.
The operation of the conventional charge pump circuit shown in FIG. 8 will be described below referring to FIGS. 9 to 11B.
In the operation mode having a voltage multiple ratio of 1 shown in FIG. 9, the P-channel MOS transistors 101 to 103 and 105 to 107 are ON, and the P-channel MOS transistor 104 and the N-channel MOS transistors 108 and 109 are OFF. The switch 113 connects the back gate of the P-channel MOS transistor 103 to the side of the input terminal 10 although this connection is not shown. In this operation mode, the input terminal 10 is connected to the output terminal 20 via the P-channel MOS transistors 101 and 105, these transistors being ON, and a voltage of 1 times the input voltage Vi is output.
In the operation mode having a voltage multiple ratio of 1.5 shown in FIGS. 10A and 10B, in the state shown in FIG. 10A, the P-channel MOS transistors 101, 106 and the N-channel MOS transistor 109 are ON, and the P-channel MOS transistors 102 to 105, the P-channel MOS transistor 107, and the N-channel MOS transistor 108 are OFF. The switch 113 connects the back gate of the P-channel MOS transistor 103 to the side of the input terminal 10 although this connection is not shown. In this state, the first flying capacitor 110 and the second flying capacitor 111 are connected in series, and the input voltage Vi is applied across both ends of the series connection. Hence, the first flying capacitor 110 and the second flying capacitor 111 are each charged to approximately half of the input voltage Vi.
In the state shown in FIG. 10B, the P-channel MOS transistors 102, 104, 105 and 107 are ON, and the P-channel MOS transistors 101, 103 and 106, and the N-channel MOS transistors 108 and 109 are OFF. The switch 113 connects the back gate of the P-channel MOS transistor 103 to the side of the second flying capacitor 111 although this connection is not shown. In this state, the first flying capacitor 110 and the second flying capacitor 111 are connected in parallel, and the low-potential side thereof is connected to the input terminal 10, and the high-potential side thereof is connected to the output terminal 20. The voltages of the two flying capacitors, amounting to approximately half of the input voltage Vi, are added to the input voltage Vi of the input terminal 10. As a result, a voltage of approximately 1.5 times the input voltage Vi is output from the output terminal 20.
Since the states shown in FIGS. 10A and 10B are repeated alternately as described above, it is possible to obtain a voltage of approximately 1.5 times the input voltage Vi from the output terminal 20.
In the operation mode having a voltage multiple ratio of 2 shown in FIGS. 11A and 11B, in the state shown in FIG. 11A, the P-channel MOS transistors 101, 103 and the N-channel MOS transistors 108 and 109 are ON, and the P-channel MOS transistors 102 and 104 to 107 are OFF. The switch 113 connects the back gate of the P-channel MOS transistor 103 to the side of the input terminal 10 although this connection is not shown. In this state, the input voltage Vi is applied to each of the first flying capacitor 110 and the second flying capacitor 111.
In the state shown in FIG. 11B, the P-channel MOS transistors 102, 104, 105 and 107 are ON, and the P-channel MOS transistors 101, 103 and 106, and the N-channel MOS transistors 108 and 109 are OFF. The switch 113 connects the back gate of the P-channel MOS transistor 103 to the side of the second flying capacitor 111 although this connection is not shown. In this state, the first flying capacitor 110 and the second flying capacitor 111 are connected in parallel, and the low-potential side thereof is connected to the input terminal 10, and the high-potential side thereof is connected to the output terminal 20. The voltages of the two flying capacitors, amounting to the input voltage Vi, are added to the input voltage Vi of the input terminal 10. As a result, a voltage of approximately 2 times the input voltage Vi is output from the output terminal 20.
Since the states shown in FIGS. 11A and 11B are repeated alternately as described above, it is possible to obtain a voltage of approximately 2 times the input voltage Vi from the output terminal 20.
In Japanese Patent Application Laid-open No. 2003-348821, a switch for switching the back gate of the P-channel MOS transistor 106 to the side of the first flying capacitor 110 or the side of the second flying capacitor 111 is described, and a sequence of switching various switches, being used to prevent through current, is explained.
The conventional charge pump circuit being configured and operating as described above is used frequently in compact and portable electronic apparatuses operating on battery power, and the components thereof are integrated in semiconductor ICs. Hence, reducing the number of switching devices being used as the components of the charge pump circuit is a very important object to be attained.